Imagine you're running the largest distributed AI training job in the world. Your model is sharded across tens of thousands of GPUs. Every millisecond counts. A single delayed packet — one lousy microsecond of congestion — can stall a collective operation, cascade into a synchronization stall, and cost you hundreds of thousands of dollars in wasted compute.
Now imagine you're not the only tenant on that cluster. Dozens of other teams are running their own jobs simultaneously on the same fabric. A bursty recommendation model in one rack is suddenly competing for bandwidth with your trillion-parameter language model in another. The network becomes a battlefield, and nobody wants to be the job that gets starved.
This is the multi-tenant nightmare at Meta scale. And solving it required rethinking how RDMA, congestion control, and scheduling interact inside a fabric that spans over 100,000 NVIDIA H100 GPUs. Let's dig into how it actually works.
The Hype, The Reality, and Why This Matters
If you've been anywhere near AI infrastructure Twitter in the last two years, you've seen the headlines: "Meta building 600,000 GPU clusters," "Zuck drops $10B on H100s," "The 100K GPU supercomputer race." Every hyperscaler has been flexing their cluster numbers, and the number that keeps coming up is 100,000+ H100s in a single training cluster, with Meta openly discussing two 24,576-GPU clusters (RSC) and plans to scale toward 350,000 H100s by end of 2024.
But here's the thing the hype cycle glosses over: raw GPU count is the easy part. NVIDIA sells you the silicon. Wrapping 100,000 of them in a network fabric that doesn't collapse under its own weight — and letting multiple teams share it without one job cannibalizing another — that's the hard part. That's where the actual engineering genius lives.
The substance behind the hype isn't "look how many GPUs we bought." It's: how do you make 100,000 GPUs behave like one deterministic machine, while safely multiplexing workloads from dozens of tenants?
Why RDMA Is Non-Negotiable
At this scale, TCP is dead on arrival. Full stop.
The reason is physics and math. Distributed training with tensor parallelism and pipeline parallelism requires GPUs to exchange gradients, activations, and parameters on the order of hundreds of gigabytes per second, with latency measured in single-digit microseconds. TCP's kernel stack — with its copies, interrupts, context switches, and congestion window ramp-up — adds tens of microseconds of overhead per packet and chokes under the fan-in of thousands of simultaneous flows.
Enter RDMA over Converged Ethernet (RoCEv2).
- Zero-copy transfers: Data goes directly from GPU memory to NIC to remote GPU memory.
- Kernel bypass: Applications talk straight to the NIC via userspace verbs (
libibverbs). - Hardware offload: The NIC handles segmentation, retransmission, and congestion signaling.
- Deterministic latency: No TCP slow start, no Nagle, no kernel scheduler.
But RoCEv2 has a dark side. It's built on Priority Flow Control (PFC) — a link-level, lossless mechanism that pauses traffic when buffers fill. PFC is notorious for two catastrophic failure modes:
- Head-of-line blocking, where one slow flow pauses an entire port.
- Congestion spreading / PFC storms / deadlocks, where pause frames cascade across the fabric and take down the whole network.
At 100K GPUs, a PFC storm is not a "degraded network" — it's a multi-million-dollar outage affecting every tenant on the fabric.
The Architecture: Clos, Rails, and the Topology Monsters
Meta's AI clusters use a rail-optimized, two-tier Clos topology. Here's the mental model:
- Each GPU server (typically 8x H100 SXM) connects via 8x 400Gbps NICs (one per GPU).
- NICs are grouped by rail — GPU 0 goes to rail-0 leaf switches, GPU 1 to rail-1, and so on.
- Leaf switches aggregate ~128-256 ports each into spine switches, which provide full bisection bandwidth.
- Two tiers: leaf (top-of-rack aggregation) and spine (fabric core). Some designs add a superspine for east-west scaling.
Why rails? Because in all-to-all collective ops (think NCCL AllReduce for a 405B parameter model), each GPU predominantly talks to the same rail index on every other server. Rail-optimized topology means those flows traverse exactly one leaf-hop, minimizing latency and hop count.
But — and here's the twist — rail optimization doesn't solve multi-tenancy. Two different jobs on the same rail still fight for the same uplinks.
The Core Problem: Performance Isolation ≠ Fairness
This is where most people get it wrong. The naive approach to multi-tenancy is "just give everyone a fair share." But fairness is not what AI training jobs need.
Training jobs are not elastic. They have hard synchronization barriers. If a single AllReduce call on one job gets throttled by 10%, the entire job slows down by 10%, because every other GPU is waiting at the barrier. There's no "catch up later."
Meanwhile, if you hard-partition the network, you waste bandwidth. A single-tenant job might only use 40% of its allocated rail capacity during non-collective phases. That idle bandwidth is pure waste.
So the goal isn't fairness. It's:
- Isolation guarantees: Job A cannot degrade Job B's tail latency.
- Work conservation: Unused bandwidth from idle jobs should be reclaimed.
- Determinism: Collective ops must not experience jitter beyond a tight bound.
These three goals are in tension. Solving them simultaneously requires custom congestion control at the NIC level.
Enter DCQCN — and Why It's Not Enough
Meta (like Microsoft, Google, and AWS) uses DCQCN (Data Center Quantized Congestion Notification) as a baseline for RoCEv2 congestion control. The mechanism:
- Switches mark packets with ECN (Explicit Congestion Notification) when queue depth exceeds a threshold.
- Receivers send CNPs (Congestion Notification Packets) back to senders.
- Senders reduce their rate based on CNP feedback, then ramp back up.
DCQCN works. It's battle-tested. But it has fundamental limitations in a multi-tenant 100K-GPU fabric:
- CNP storms: At 100K endpoints, a single congestion event can trigger millions of CNPs, overwhelming the reverse path.
- Rate oscillation: DCQCN's AIMD-style ramp causes throughput to swing wildly under high fan-in.
- No tenant awareness: DCQCN doesn't know or care whose flow it's throttling. A bursty tenant can starve a latency-sensitive one.
- Slow convergence: Under incast patterns typical of AllReduce, DCQCN takes milliseconds to stabilize — an eternity at this scale.
Meta's answer: build congestion control that understands tenants, understands collective patterns, and operates at microsecond granularity.
The Custom Stack: Multi-Tenant RDMA with Tenant-Aware Congestion Control
Here's the secret sauce. Meta's fabric isn't just running DCQCN anymore. It's running a hybrid, tenant-aware congestion control framework that layers three innovations.
1. Virtual Lanes with Hardware Rate Limiting
Each tenant's traffic is assigned to a Virtual Lane (VL) at the NIC level. The NIC enforces a hard rate ceiling per VL in hardware — think of it as a token bucket that lives in silicon, not software.
VL 0 (Tenant A): max 320 Gbps, priority 5
VL 1 (Tenant B): max 240 Gbps, priority 3
VL 2 (Tenant C): max 400 Gbps, priority 7
Because the rate limiting is in hardware, it can respond in nanoseconds, not microseconds. A misbehaving tenant literally cannot exceed its ceiling, no matter how aggressive its RDMA queue pairs become.
The kicker: ceilings are dynamic. When a tenant's job enters a non-collective phase (e.g., optimizer step on CPU), its unused tokens are temporarily loaned to other VLs. This is work conservation without sacrificing isolation.
2. Collective-Aware Congestion Signaling
Meta's stack detects when a tenant is running a known collective pattern (ring AllReduce, tree AllGather, etc.) and pre-provisions bandwidth along the expected path. This is done via a lightweight control plane agent on each node that:
- Interrogates NCCL for the current collective type.
- Predicts the fan-out pattern based on rank topology.
- Sends bandwidth reservations to the involved leaf switches.
The result: instead of reacting to congestion, the fabric anticipates it. Latency jitter on collective ops drops by up to 4x compared to pure DCQCN in production traces.
3. ECN with Tenant-Aware Weighting
When ECN marking does fire, the switch is now tenant-aware. Instead of marking all packets equally, it weights marks by:
- Tenant priority (higher priority = fewer marks).
- Current rate (greedy flows get marked more aggressively).
- Flow age (long-running elephant flows get marked more than short mice).
This is implemented via P4-programmable switches (likely Tofino-class) that run a custom ECN policy in the data plane. The logic looks roughly like:
action mark_ecn_with_weight(tenant_id, flow_rate, flow_age) {
weight = priority_table[tenant_id]
* rate_penalty[flow_rate]
* age_penalty[flow_age];
if (random() < weight * base_mark_prob) {
mark_packet_ecn();
}
}
The effect: a tenant running a latency-sensitive inference workload gets gentler marking, while a bulk gradient sync gets throttled harder — even if both are equally congesting the fabric.
The Scheduler: Admission Control at 100K Scale
Congestion control is only half the story. The other half is deciding who gets to run when.
Meta's cluster scheduler (a descendant of Tupperware and Twine, evolved for AI) does topology-aware admission control:
- Jobs declare their communication profile (collective-heavy, point-to-point, sparse).
- The scheduler checks whether the fabric has enough isolated capacity to admit the job.
- If not, the job is queued — even if GPUs are free.
This is a radical departure from traditional HPC schedulers, which greedily pack jobs onto idle hardware. At Meta's scale, a job that fits on GPUs may not fit on the network, and admitting it anyway would tank the performance of every tenant already running.
The scheduler also exploits spatial isolation:
- Small jobs (< 512 GPUs) are packed into a single leaf subtree, so their traffic never touches the spine.
- Large jobs get dedicated spine slices with reserved bandwidth.
- Gang scheduling ensures all ranks of a job start within milliseconds of each other.
Real Numbers: What Does This Actually Buy You?
Meta has been relatively tight-lipped about exact benchmarks, but publicly discussed figures from their Llama 3 405B training on 16,384 H100s give us a window:
- Effective MFU (Model FLOPs Utilization) above 38% at 16K GPU scale — an industry-leading number.
- NCCL AllReduce efficiency > 90% of theoretical bisection bandwidth.
- P99 latency jitter on collective ops reduced from ~15% to under 4% with tenant-aware ECN.
- Multi-tenant slowdown on co-located jobs limited to < 5% at the 75th percentile — versus > 30% on naive setups.
Translated to business impact: on a 24,576-GPU cluster, a 5% slowdown prevented is worth tens of millions of dollars per year in reclaimed training throughput.
The Engineering Curiosities Nobody Talks About
A few details that reveal just how deep this rabbit hole goes:
Optical circuit switching for elasticity. Meta has experimented with optical circuit switches (OCS) in their AI fabric to reconfigure topology on the fly — literally rerouting light to reshape the network between training phases. This lets them create transient "super-rail" topologies for specific collective patterns.
Per-GPU telemetry at 100K endpoints. Every NIC emits flow-level telemetry at 10 microsecond resolution. That's **10^11 data points per second** streaming into a custom time-series backend. The volume alone required new storage primitives.
Silent data corruption detection. At 400Gbps per NIC, a single bit flip in a gradient packet can poison an entire training step. Meta's fabric uses end-to-end CRCs in the RDMA payload, not just at the Ethernet layer, so corruption is caught before it reaches the optimizer.
The "brownout" protocol. When a spine link degrades (fiber cut, overheating ASIC), the fabric enters a graceful degradation mode where low-priority tenants are preemptively throttled to protect high-priority jobs. This is coordinated by a fabric-wide control loop running at ~100ms cadence.
NCCL is a first-class citizen. Meta upstreamed major NCCL optimizations — including topology-aware ring construction and collnet integration for in-network reduction — specifically so their custom congestion control could hook into collective scheduling. This isn't a fork-and-forget; it's a deep co-design.
What This Means for the Rest of Us
You're probably not running 100K H100s. But the principles scale down beautifully:
- Don't trust fairness — engineer isolation. Rate limiting in hardware beats software fairness every time.
- Congestion control should know your workload. Generic AIMD is a blunt instrument. If your workloads have predictable patterns, encode them.
- The scheduler must understand topology. Admitting a job onto a network that can't carry it is worse than making it wait.
- Work conservation and isolation are not opposites. Dynamic VL borrowing shows you can have both with the right primitives.
- Measure tail latency, not average. Training jobs care about P99, not median.
Even a 100-GPU cluster running Ray or Kubernetes can adopt tenant-aware ECN (many modern NICs support DCQCN configuration) and topology-aware scheduling (Kueue, Volcano). The Meta playbook is aspirational, but its ideas are portable.
The Road Ahead
The next frontier is photonic fabrics with dynamic topology reconfiguration, integrated with hierarchical congestion control that spans DC, regional, and edge AI training. Meta has hinted at gigawatt-scale clusters with 500K+ accelerators, likely next-generation NVIDIA Blackwell or custom silicon (MTIA).
At that scale, the network is the computer. And the teams who figure out how to slice it deterministically for dozens of tenants at once will be the ones shipping the models that define the next decade of AI.
The GPUs get the headlines. But the fabric — and the beautiful, gnarly, deeply unglamorous congestion control running inside it — is what makes them sing.
Got thoughts on RDMA, congestion control, or multi-tenant AI fabrics? The comments are open. Let's geek out.